WG 5: Validation, Evaluation, and Fault Injection

WG Leaders

This WG is focused on the following issues:

1. Fault-injection campaigns
The effect of laser shots into circuits will be evaluated to obtain statistically significant data on the consequences of the attacks. For that, experiments will be performed on commercial available circuits (for instance FPGAs), and circuits already available in the partners’ labs. Precise models of the laser shots onto the circuit will be modeled from the conducted experiments.

2. Fault simulators for realistic fault-models
To simulate faults at different levels of abstraction (transistor, gate, register-transfer, system level), there are several methods for efficient fault simulation, including compiled, event-driven, emulated, parallel and deductive techniques. Although a variety of commercial tools are available for this purpose, they do not provide access to detailed information required in security context. One goal of this Action will be to assist in developing, by multiple involved group members, an open-source simulator able to perform both logic and fault simulation for realistic fault models extracted from the fault-injection campaigns described above. The fault injector will be enhanced by an FPGA-based emulation platform.

3. Validation
Formal verification methods that mathematically prove immunity to certain classes of malicious faults will be investigated, by using for instance techniques based on Boolean Satisfiability and Quantified Boolean Formula solvers. Accurate modeling of malicious faults is important because advanced redundancy mechanisms are developed by the information theory community and evaluated using high-level metrics, which do not capture circuit aspects. The extensive work on fault modeling that has been performed by the test community will be used to assess whether the properties of the redundant codes reported by the information theory community can be confirmed in application.

4. Evaluation
Cryptographic Engineering takes up all aspects for implementation of cryptographic algorithms in hardware (and/or software). This ranges from implementations with high performance demands implementations with hardware resource restrictions and ultra-low power implementations of cryptographic primitives, fault tolerant implementations, attack resistant implementation and implementations of attacks. This task focuses on the hardware evaluation of the cryptographic and safety solutions. Hardware measurements will be given in terms of performances, power dissipation, and amount of used hardware resources.

Working Group Participants

Name Country Email
Chairs: Lejla Batina NL lejla@cs.ru.nl
Nicolas Sklavos GR nsklavos@ieee.org
Members:
1 Lilian Bossuet FR lilian.bossuet@univ-st-etienne.fr
2 Zebo Peng SE zebo.peng@liu.se
3 Bernd Becker DE becker@informatik.uni-freiburg.de
4 Paris Kitsos GR pkitsos@eap.gr
5 Artemios Voyiatzis GR bogart@isi.gr
6 Julien Francq FR Julien.Francq@cassidian.com
7 Assia Tria FR tria@emse.fr
8 Ilia Polian DE ilia.polian@uni-passau.de
9 Nele Mentens BE Nele.Mentens@esat.kuleuven.be
10 Guy Gogniat FR guy.gogniat@univ-ubs.fr
11 David Hély FR david.hely@lcis.grenoble-inp.fr
12 Bruno Rouzeyre FR rouzeyre@lirmm.fr
13 Said HAMDIOUI NL S.Hamdioui@tudelft.nl
14 Philippe Loubet Moundi FR Philippe.LOUBET-MOUNDI@gemalto.com
15 Viktor FISCHER FR fischer@univ-st-etienne.fr
16 Marie-Lise FLOTTES FR flottes@lirmm.fr
17 Francesco Regazzoni CH regazzoni@alari.ch
18 Paolo Maistrii FR paolo.maistri@imag.fr
19 Tim Güneysu DE tim.gueneysu@ruhr-uni-bochum.de
20 Franck Courbon FR Franck.Courbon@gemalto.com
21 Róbert Lórencz CZ lorencz@fit.cvut.cz
22 Noemie Boher FR noemie.boher@lcis.grenoble-inp.fr
23 Apostolos Fournaris GR apofour@ece.upatras.gr
24 Tomáš Vaňát CZ tomas.vanat@fit.cvut.cz
25 Jan Pospíšil CZ jan.pospisil@fit.cvut.cz
26 Louiza Papachristodolou NL louizap@cs.ru.nl
27 Alexander Wild DE alexander.wild@rub.de
28 Ileana Buhan
Others:
1 Osnat Keren IL osnat.keren@biu.ac.il
2 Carles Ferrer ES carles.ferrer@uab.cat
3 Pedro Peris-Lopez ES pperis@inf.uc3m.es
4 Milos Drutarovsky SK Milos.Drutarovsky@tuke.sk
5 Viacheslav Izosimov SE Viacheslav.Izosimov@eis.semcon.com
6 Giorgio Di Natale FR giorgio.dinatale@lirmm.fr
7 Salvador Manich ES salvador.manich@upc.edu
8 Jean-Luc Danger FR jean-luc.danger@telecom-paristech.fr
9 Sylvain Guilley FR sylvain.guilley@telecom-paristech.fr
10 Shivam Bhasin FR shivam.bhasin@telecom-paristech.fr
11 Olivier Rioul FR olivier.rioul@telecom-paristech.fr