WG1 Manufacturing test of secure devices

WG Leaders

  • Marie-liseFlottes, LIRMM, flottes[at]lirmm.fr
  • Said Hamdioui, Delft U. of Technology, S.Hamdioui[at]tudelft.nl

This WG is focused on the following issues:

1. Tools and methodologies to improve test production coverage for secure functions
Classical techniques for digital circuit testing cannot be easily used for testing of secure devices. They are based on Design-for-testability techniques that add hardware components to the circuit, aiming to provide full controllability and observability of the internal states. Because crypto-processors and other cores in a secure system must pass through high-quality test procedures to ensure that data are correctly processed, testing of crypto chips faces a dilemma. Design-for-testability schemes require high controllability and observability of the device while security necessitates minimal controllability and observability in order to better hide the secret information. Developing innovative design-for-testability techniques and test methods becomes therefore a fundamental task for manufacturing high quality secure devices.

2. Secure protocols and controllers to protect the access to necessary test infrastructures
Typical test access points are inputs and outputs of scan chains, JTAG (Joint Test Action Group) port and other mechanisms. Reinforcing the protection based on the differentiation of the test mode from the user mode is the proposed approach in the academic world. Its integration in real secure devices is still an issue. Therefore, new secure test protocols based on the use of enhanced test controllers must be investigated. Moreover, access strategies might change during the lifetime of the device and this must be taken into account.

3. Extending security for IEEE system-level test standards
Test standards like IEEE 1149 and IEEE 1500 do not explicitly take into account security issues. One important aspect of this Action is the opportunity of joining the knowledge of academic and industrial researchers to integrate security in current standards.

Working Group Participants

Name Country Email
 Chairs: Marie-Lise FLOTTES FR flottes@lirmm.fr
 Said HAMDIOUI NL  S.Hamdioui@tudelft.nl
Members:
1 Nicolas Sklavos GR nsklavos@ieee.org
2 Lejla Batina NL lejla@cs.ru.nl
3 Nele Mentens BE Nele.Mentens@esat.kuleuven.be
4 David Hély FR david.hely@lcis.grenoble-inp.fr
5 Bruno Rouzeyre FR rouzeyre@lirmm.fr
6 Francesco Regazzoni CH regazzoni@alari.ch
7 Viacheslav Izosimov SE Viacheslav.Izosimov@eis.semcon.com
8 Urban Ingelsson SE urban.ingelsson@semcon.com
9 Salvador Manich ES salvador.manich@upc.edu
10 Giorgio Di Natale FR giorgio.dinatale@lirmm.fr
11 Paul Henri Pugliesi Conti FR paul-henri.pugliesi-conti@nxp.com
12 Ilia Polian DE ilia.polian@uni-passau.de
13 Ingrid Verbauwhede BE ingrid.verbauwhede@esat.kuleuven.be
14 David Hernandez ES david.hernandez.g@applus.com
Others:
1 Lilian Bossuet FR lilian.bossuet@univ-st-etienne.fr
2 Bernd Becker DE becker@informatik.uni-freiburg.de
3 Paris Kitsos GR pkitsos@eap.gr
4 Osnat Keren IL osnat.keren@biu.ac.il
5 Julien Francq FR Julien.Francq@cassidian.com
6 Assia Tria FR tria@emse.fr
7 Guy Gogniat FR guy.gogniat@univ-ubs.fr
8 Carles Ferrer ES carles.ferrer@uab.cat
9 Pedro Peris-Lopez ES pperis@inf.uc3m.es
10 Philippe Loubet Moundi FR Philippe.LOUBET-MOUNDI@gemalto.com
11 Geert-Jan Schrijen NL Geert.Jan.Schrijen@INTRINSIC-ID.COM
12 Vincent van der Leest NL Vincent.van.der.Leest@intrinsic-id.com
13 Milos Drutarovsky SK Milos.Drutarovsky@tuke.sk
14 Viktor FISCHER FR fischer@univ-st-etienne.fr
15 Tim Güneysu DE tim.gueneysu@ruhr-uni-bochum.de
16 Franck Courbon FR Franck.Courbon@gemalto.com
17 Róbert Lórencz CZ lorencz@fit.cvut.cz