Main/primary objectives

The aim of the Action is to identify new design and manufacturing flows for the production of secure integrated circuits by creating a strong network between several centers of expertise on hardware security at European level, and to substantially increase the level of cooperation and consequent visibility of European research on this vital topic.

Secondary objectives

The main objectives of this Action are (i) the knowledge creation to respond to new issues, and (ii) the consolidation of the scientific excellence in the target domain through the integration of the research skills of the participants.

From a scientific perspective, this project targets the following goals:

  • To provide solutions for required but conflicting relationships between Testability and Security. The expected impact is a new generation of more secure and more testable products in a field where European IC industry has a leadership position to maintain
  • To develop innovative design-for-testability Computer-Aided Design (CAD) tools for supporting security issues and with a specific attention to compliance with existing commercial tools
  • To define secure protocols to protect the access to necessary test infrastructures and to design secure access controllers
  • To contribute in the definition of new test standards that intrinsically include security issues
  • To study new mechanisms for devices identification and authentication based on the usage of Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs)
  • To address issues related to counterfeiting and Hardware Trojan insertion and to propose new methods and algorithms for their identification
  • To define new architectures able to detect faults and to resist to fault attacks
  • To establish a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks
  • To explore implementation and security issues of cryptographic logic based on Field-Programmable Gate Array (FPGA)
  • To collect statistically significant data related to fault injection campaigns
  • To explore formal verification methods to establish the robustness of a secure device against fault attacks

From the networking point of view, this Action is anticipated to aid towards the development of early-stage faculty researchers into experts in their respective fields, and improve the knowledge and skills of Ph. D. students and post-doctoral fellows, which will enable them to perform high-quality research. Moreover, it will support mobility between participating research centers, both of senior researchers to foster exchange of ideas through short term visits, and of junior researchers/PhD students to enable the exchange of technical knowledge through longer term visits.

Dissemination activities will be carried out by joint papers in international journals and conference proceedings, and through the organization of special sessions at international conferences.